1. Field of the Invention
The present invention relates to a stabilized current mirror circuit.
2. Description of the Related Art
FIG. 5 shows a prior art current mirror circuit.
Current mirror circuit 10 consists of input-stage nMOS transistor 11 which has the diode connection and output-stage nMOS transistor 12. Current I1 is provided to nMOS transistor 11 as an input signal. The output current I2 of current mirror circuit 10 is also the input for the pMOS transistor 21 which has the diode connection. pMOS transistor 21, for example, is also an input-stage for another current mirror circuit, and gate potential VB of pMOS transistor 21, in this case, is provided to the gate of a pMOS transistor (not illustrated) on the output-stage of this current mirror circuit.
In an ideal case where nMOS transistors 11 and 12 have the same characteristics and output potential V2 (Drain potential) of nMOS transistor 12 is equal to drain potential V1 of nMOS transistor 11, I1 is equal to I2. However, as described below, V1 and V2 are not equal in general.
Since nMOS transistor 11 has the diode connection, namely its gate is short-circuited to its drain, drain voltage V1 is about the threshold voltage Vthn of nMOS transistor 11. Since pMOS transistor 21 has also the diode connection, drain voltage (VDD-V2) of pMOS transistor 21 is about Vthp which is the absolute value of the threshold voltage of pMOS transistor 21.
As a general numeric example, if VDD=3.0 V, and Vthn=Vthp=1.0 V, then, V1=1.0 V and V2=2.0 V, and thus, I1&lt;I2.
Establishing V1=V2 and I1=I2 is an ideal example, and generally it is ideal to make constant the transfer characteristics of current mirror circuits, namely to have no variations in those characteristics.
However, if threshold voltage Vthp is varied or the saturation characteristics of MOS transistors are changed due to variations in the manufacturing processes, there exist variations in the output potentials of current mirror circuits. The variations of output potential V2 due to that becomes conspicuous according to the miniaturization of the circuit elements of integrated circuits. Also, output potential V2 is affected by variations in power supply voltage VDD or temperature.